15 years ago, our friend Mike Bryant, CTO of Future Horizons, gave a tour d’horizon of the future of semiconductor process technology at the IFS-MT2010 conference in London,
First of all Bryant tackled the problems:
“The cost of developing a process node is inversely proportional to the node length,” said Bryant, “so the cost of developing 22nm is twice that of 45nm which cost twice the 90nm development cost.”
The second big problem is that the cost of producing a design is nearly proportional to the transistor density of the process used – the doubling of transistor density increases design cost 1.9X.
Despite these trends, the price per sq cm of processed silicon remains constant at $9, pointed out Bryant.
Or you could calculate it as Gordon Moore sometimes liked to do as a billion dollars an acre.
Clearly silicon-based CMOS is coming to an end, asserted Bryant.
“There is no reliable transistor yet for 16nm”, said Bryant, “and by the time 10nm comes, the effects of Quantum Mechanics will be dominating Newtonian physics.”
This is not a trivial matter. Bryant quoted Niels Bohr’s remark that: ‘Anyone who does not have a headache after first encountering quantum mechanics clearly has not understood a thing.”
“The variability and unpredictably of electron clouds will have to be taken into account at the RTL level,” said Bryant, “digital circuits will need to be fundamentally fault tolerant, and analogue alternatives may become viable again.”
Addressing the alternatives to silicon-based CMOS, Bryant suggested:
“A strontium-germanium interlayer between a hi-k insulator and a germanium channel gives several more generations.” Which might, unfortunately, add ten extra processing steps to the manufacturing process, or:
“III-IV materials are another option but are less compatible with existing processes.”
They also, he said, would be very expensive.
Another alternative to silicon-based CMOS, continued Bryant, is to use carbon-based transistors.
“Carbon transistors, built on a silicon substrate, can take us to the molecular level,” said Bryant, “three weeks ago a group managed to grow grapheme across a six inch wafer.”
C60 nanotubes and graphene have excellent conductive properties, he pointed out, while standard metal lines down to 4nm are not a major problem.
“Nanotube, graphene and diamond transistors have been demonstrated,” said Byant, “single atom transistors have been demonstrated using various compounds, but the carbon-based benzene ring is probably the smallest reliably usable switching block.”
This will be the absolute scaling limit, said Bryant, but it doesn’t mean the end of Moore’s Law.
By the time the benzene ring is being used as a switching element, 3D structures will be commonplace.
“So the absolute transistor limit is almost infinite”, said Bryant.
By 3D, Bryant means true 3D on a single die – not stacked die. And here the number of processing steps will be the practical limit.
“SOC designs will have to be either fully fault tolerant or reconfigurable to work around the faults that are bound to occur,” said Bryant.
The average die size will increase significantly to get all the required connections off the die.
“Despite the use of the term System On Chip, our current ICs are anything but, and the number of connections required to interface with the rest of the system seem to rise almost as fast as Moore’s Law,” said Bryant.
An alternative to the 3D approach is to get more from each transistor using purely quantum mechanics based solutions.
“These operate on different laws of physics to conventional semiconductors and are still in their infancy,” said Bryant, “platforms for possible quantum computers include superconductors, trapped ion, fullerenes, optical, molecules in solution and many more.”
Silicon will remain the platform for all these alternative futures. And it will remain the platform until nano-biotechnology replaces it.
Engineered proteins will then become the building blocks and, though delivering larger, slower systems, they will use far less power than semiconductors could ever achieve.
So, leakage, cost and interconnection complexity are not going to spell the end of this particular story, concluded Bryant, the days of silicon-based CMOS may be numbered, but not the days of Moore’s Law.
Earlier this week I asked Mike what he thought of his 15 year-old observations, and this is is what he replied:
“We did put SiGe (no strontium – got that wrong) and III-V deposits into the transistors using ASM’s (not ASML) new deposition techniques.
And Imec’s CFET is a first step towards the 3D I envisioned.
And the $9/sq cm eventually was dropped by everyone else as well as Intel. TSMC’s new wafer pricing saw to that.
But we seem to still be managing to avoid carbon even at 1.4nm. Maybe one day.
And I still don’t understand how quantum mechanics doesn’t make 3nm transistors unworkable. Even Prof Asen Asenov hasn’t been able to explain that one to me. I do wonder how much error-correction is built into modern designs.”
